| 摘要 |
<p>OPTIMAL DRIVER FOR LSI An intermediate driver circuit comprising at least five stages which are cascaded between a signal driver, such as a logic circuit on an LSI chip, and a high capacity load driver, such as a driver for long off chip interconnection lines, wherein the total delay in the signal source caused by great disparity between the capacitance of the signal driver and the load driver is minimized. The delay is minimized by use of a cascaded series of n-intermediate drivers where n=lnM, M = , and where the capacitance of any intermediate stage is . Use of these parameters in the design of intermediate stages, each having a capacitance designed in accordance with the foregoing equations has been found to be useful in connection with amplifiers having five or more intermediate stages, and wherein the ratio of capacitance of the load circuit to the capacitance of the driver circuit is greater than about one hundred to one. The utility of these design parameters in instances where the ratio of capacitance is greater than a thousand to one, and the number of intermediate stages is ten or greater is particularly apparent.</p> |
