| 摘要 |
PURPOSE:To allow a circuit scale to be small, to contrive a cost reduction, and simultaneously, to enhance reliability by providing an address counter for writing data, an address counter for reading data, a 2-port memory and a +2 adder. CONSTITUTION:An address counter 2 for writing data and an address counter 3 for reading data are operated by a data writing clock 7 and a data reading clock 8 to be mutually independent, respectively. A +2 adder 4 adds 2 to the most significant 2 bits of the counter 2 at the time of initializing the circuit and sets the low-order 2 bits of an added result at the most significant 2 bits of the counter 3. The address space of a 2-port memory 1 to have two ports of data ports and address ports, respectively, is divided into four to be used. In such a case, as long as the address values of two ports do not coincide, the data are independently written and read, a Doppler buffer circuit is physically composed of a single memory, the circuit scale can be miniaturized the cost is reduced, and simultaneously, the reliability can be enhanced. |
