发明名称 STAMPED LEAD FRAME FOR SEMICONDUCTOR PACKAGES
摘要 A stamped, 40-lead ceramic dual-in-line package (Cer-Dip) frame is disclosed. Increased usage and lowered costs of large scale, integrated circuits (LSI) for microprocessor and similar applications has created a demand for precision ceramic packaging of the forty-lead dual-in-line type that is adapted for automated chip insertion in high-volume and at a low cost. The present invention meets this need with a stamped lead frame wherein the longest and most fragile leads are held in precise spatial relation by means of break-off tabs. After embedment of the leads on the ceramic substrate with a glass composition, the tabs are broken and removed. Forming, scoring and bending of the tabs are carried out as an integral part of the progressive stamping operation. Lead frames according to the invention replace much more expensive etched parts. The invention may be applied in a variety of packages.
申请公布号 GB1571173(A) 申请公布日期 1980.07.09
申请号 GB19780010423 申请日期 1978.03.16
申请人 PLESSEY INC 发明人
分类号 H01L23/50;H01L21/48;H01L23/495;(IPC1-7):01L23/48 主分类号 H01L23/50
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