Programmer for implanted pacer

摘要

A plurality of programming bits are placed into a parallel in-serially out register. When the programmer is activated, a monostable resets a counter, and energizes an oscillator which clocks the counter. Three subintervals from the counter are utilized for pulse width modulation of the programming signals. Once for each bit, the output is energized and begins transmitting pulses at the lowest subinterval rate. Depending upon the logic state of each bit, the transmission pulse is terminated either at the second or the third subinterval time.