BIT DELAY DETECTOR FOR SERIES DATA

摘要

PURPOSE:To make it possible to detect the bit delay of information passing through a slave transmitter-receiver by circularly shifting the contents of either of two used shift register and then by counting the number of shifting until both contents agree each other. CONSTITUTION:When data are inputted to shift registers 1 and 2, ''1'' is added to switching pulse L5 and shift clock L2 is supplied, so that transmitted data L1 and L4 will be inputted to registers 1 and 2. Next, setting pulse L5 to zero supplies shift clock L3 to register 2 and data overflowing from register 2 are inputted through OR gate 12. Further, counter 5 counts the number of clocks L3. Once the contents of registers 1 and 2 agree each other, a coincidence output from comparator 3 resets FF5 to stop the operation of counter 4. Judging from the count number, it can be found how many bits the content of register 1 advances from that of register 2.