发明名称 Phase locked loop set=up - synchronises reference signal to input signal by using amplitude samples of reference signal as measure of phase
摘要 <p>The phase locked loop derives sample pulses from the edge changes in the input signal and uses them to sample the instantaneous amplitude of the reference signal. This amplitude bears a given relationship to the phase of the reference signal and is used as a measure of the difference between the input and reference signal for forming the control signal that controls the voltage-controlled oscillator. The reference signal may be sinusoidal, triangular, or an asymmetric sawtooth. The control input of the phase detector is connected to a stage that shapes the sample pulses. A hold capacitor is charged to a wanted value by several samples of the reference signal's amplitude.</p>
申请公布号 DE2854039(A1) 申请公布日期 1980.07.03
申请号 DE19782854039 申请日期 1978.12.12
申请人 HEINRICH-HERTZ-INSTITUT FUER NACHRICHTENTECHNIK BERLIN GMBH 发明人 HEYDT,GUENTER,ING.
分类号 H03L7/091;H04L7/033;(IPC1-7):03K1/17;04L7/00;04L25/40;03B3/04 主分类号 H03L7/091
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