发明名称 ABNORMALITY PROCESSING SYSTEM OF COMPUTER CONTROL SYSTEM
摘要 PURPOSE:To prevent the breakdown of memory contents and the generation of an error signal by stopping the operation of an access function unit by a hardware method right before a reset signal is outputted to the common bus of a computer control system when restarting the system after the occurrence of abnormality. CONSTITUTION:Direct memory access units DMA1-DMAn providing the data transmission and reception to and from memory MEM independent of processor CPU are connected to common bus BUS and bus controller BCNT controls this bus BUS. In this controller BCNT, bus output circuit DR2 generating a stop command signal for units DMA1-DMAn is provided in addition to bus output circuit DR1 connected to delay circuit DLY. Then, when abnormality sequence control part CONT2 of power-supply supervisory control part PCNT detects abnormality, the operations of units DMA1 to DMAn are stopped right before a reset signal is output from outputs of circuit DR2 and circuit DR1 to bus BUS, and the reset signal is outputted after all-operation stop.
申请公布号 JPS5588146(A) 申请公布日期 1980.07.03
申请号 JP19780162288 申请日期 1978.12.27
申请人 FUJI ELECTRIC CO LTD 发明人 ADACHI HIROSHI
分类号 G06F11/14;G06F11/00;G06F13/28 主分类号 G06F11/14
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