发明名称 MEMORY CONTROL SYSTEM
摘要 PURPOSE:To realize the connection of a kind of the memory card to each CPU by giving the refreshment to two kinds of CPU's with the refresh signal and the chip enable signal. CONSTITUTION:In case the memory card is connected to the 1st CPU, therminal C features logic 1. Timing circuit 2 is inactive when no refresh signal (a) arrives at terminal A. When chip enable signal (b) is supplied to terminal B, signal R/W is delivered from OR circuit 5 to actuate the memory. When signal (a) arrives at terminal A, the signal is transmitted twice from circuit 5 via the output of circuit 2. Then the address designation is given at FF6, and the two addresses of the memory chip are refreshed. While with connection of the card to the 2nd CPU, terminal C features 0. And the refreshment is given when signal (b) arrives at terminal B.
申请公布号 JPS5587382(A) 申请公布日期 1980.07.02
申请号 JP19780159150 申请日期 1978.12.26
申请人 FUJITSU LTD 发明人 IZAWA EIICHI;IGI YOUZOU
分类号 G11C11/406 主分类号 G11C11/406
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