| 摘要 |
PURPOSE:To reduce the cycle time via the device featuring the easy manufacture by providing plural units of the memory circuit and then giving the time division to the information read out of those memory circuits in parallel via the corresponding address register to then carry out the serial output. CONSTITUTION:When the address signals of different LSB bits are supplied twice and continuously in address decoder 4 during the reading cycle time, address registers 61 and 62 are controlled by control circuit 7. Thus the data are read out in overlap and parallel from RAM31 and 32 in accordance with the addresses stored in registers 61 and 62. These data read out receive the time division via data multiplexer 9 controlled by read selection signal RS given from circuit 7 to be delivered in series. Accordingly, two sets of RAM's are read out at one time during the 1-time reading period, and thus the reading cycle is reduced substantially down to 1/2. |
