发明名称 PROCESSING SYSTEM FOR INTERRUPTION INPUT
摘要 PURPOSE:To enable high speed transmission in low cost, by providing the control unit delivering the interruption input board to a given address. CONSTITUTION:The control unit 11 registrates the address of a given address of CPU of the register REG corresponding to the input boards 21-2m outputting the interruption input in response to the request of CPU requiring the interruption input among CPU11-CPU14. The control unit 11 references the content of registration of REG corresponding to the address data with the address data given to the interruption input and determines the delivered address when the interruption input is produced, and delivers the interruption input from the input board designated to a given CPU.
申请公布号 JPS5585939(A) 申请公布日期 1980.06.28
申请号 JP19780158829 申请日期 1978.12.22
申请人 TOKYO SHIBAURA ELECTRIC CO 发明人 TANAKA HIROSHI;URUSHIBATA YUKIO
分类号 G06F13/24;G06F3/00;G06F13/00;G06F15/16;G06F15/173;G06F15/177 主分类号 G06F13/24
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