Quartz clock with analogue display and rapid resetting - has correction pulses supplied via logic network for increased motor rotation

摘要

The quartz clock has the quart oscillator pulses supplied via electronic frequency dividers to a motor driving the analogue display. The motor has a drive winding and a control winding with a bistable circuit receiving pulses derived from the frequency dividers and from the motor, its output controlling a switching circuit for allowing rotation of the display at an increased rate. A NO-AND gate receives the output of the bistable circuit and an additional frequency divider, the gate output supplied via an FET amplifier and a resistor to the motor drive winding.