| 摘要 |
<p>A programmable logic array (PLA) comprising a search array in which the logical AND of one or more inputs (product terms) is formed and coupled to a read array in which each output is formed from a logical OR of one or more of the inputs (58) from the search array. The read array has a plurality of output circuits (70, 71, 72) each including a plurality of gates (one gate for each product term input), a load device (84) and an output connection.</p><p>The positions of inputs (58) are selected so that a plurality of inputs to output circuits (70,71,72) are juxtaposed and connected to gates in a single column. All gates are placed in a minimum of two columns with loads (84) in an adjacent column. The two columnlayout allows the inputs to overlap.</p><p>In an alternative two column layout, used when an input requires connection to a plurality of output circuits, one of the columns is devoted to a column conductor interconnecting gates.</p><p>Outputs are taken from the side, top and bottom of the array. This layout minimizes the area of chip required for the read array and produces improved performance.</p> |
