发明名称 CONTROL SYSTEM FOR CLOCK SIGNAL DISTRIBUTION CIRCUIT
摘要 <p>PURPOSE:To cause the oscillation through the short-circuit given between the input and output ends of the transmission line in the fixed length and by constituting the distribution circuit so that the opposite phase may be secured for the input and output ends to each other, and then to give the control to the transmission line delay amount to secure the fixed frequency while measuring the oscillation frequency through the counter. CONSTITUTION:The control is given in accordance with the fixed value to the delay time from the input to output end of distribution circuit 5 which distributes the clock signals sent from clock signal generation source 7 to plural units of load circuit 4. Circuit 5 possesses the delay time variable means and is formed so that the opposite phase may be secured for the signals between the input and output ends to each other. For the control, the short circuit is given between the input and output ends via the line featuring the fixed delay time to cause the oscillation. And then the delay time variable means is controlled to secure the prescribed value for the oscillation frequency.</p>
申请公布号 JPS5583913(A) 申请公布日期 1980.06.24
申请号 JP19780158898 申请日期 1978.12.20
申请人 FUJITSU LTD 发明人 YOSHIMURA TATSUROU
分类号 G06F1/10;G01R31/3183;H03K5/15 主分类号 G06F1/10
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