发明名称 DECODER CIRCUIT
摘要 PURPOSE:To omit the exclusive logic for suppression of the ineffective output by adding the 1-bit parity bit as well as installing the OR circuit, at the same time ensuring the immediate use of the effective output. CONSTITUTION:Decoder 205 delivers the output of 2<m+1> bits to the input of total m+1 bits of significant bits I1-Im and parity bit IP. Among these output, the 2<m> bits (ineffective output) which is delivered when the parity error exists in the m+1 bit input is supplied to OR circuit 206. The rest 2<m> bits are the effective output to m-bit input I1-Im and delivered when no parity error exists to m+1 bit input I1-Im plus IP. Thus the ineffective output to the input containing the parity error is never transmitted outside, and as a result the exclusive logic can be omitted for suppression of the ineffective output. At the same time, the effective output can be used immediately.
申请公布号 JPS5584091(A) 申请公布日期 1980.06.24
申请号 JP19780156395 申请日期 1978.12.20
申请人 HITACHI LTD 发明人 MORITA MASATO;NAGAI TOMONORI
分类号 H03M7/00;G06F11/10;G11C8/10 主分类号 H03M7/00
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