发明名称 |
DIGITAL MULTIPLIER |
摘要 |
A round off correction logic circuit is disclosed for inclusion within a floating point arithmetic binary digital multiplier implementing a modified Booth's algorithm for generating a final product of binary digits. The round off logic circuitry is connected in the multiplier for rounding its final product off to a predetermined binary digit without requiring the multiplier to generate any of the less significant binary digits to the right of the predetermined binary digit. Multiplier circuitry otherwise required to generate an unrounded final product prior to round off is eliminated without loss of accuracy in round off. |
申请公布号 |
JPS5582354(A) |
申请公布日期 |
1980.06.21 |
申请号 |
JP19790153071 |
申请日期 |
1979.11.28 |
申请人 |
AMERICAN MICRO SYST |
发明人 |
ROOBUITSUKU GUREGORIAN;KADEIRI RAMACHIYANOORA REDEII |
分类号 |
G06F7/38;G06F7/483;G06F7/508;G06F7/52;G06F7/53;G06F7/533 |
主分类号 |
G06F7/38 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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