发明名称 DATA PROCESSOR
摘要 PURPOSE:To execute the transmission and reception of a packet at high speed by selecting a FIFO memory corresponding to a transmitting page on the basis of page control information from the respective FIFO memories in the side of a packet transmitting part, transferring an address according to the page control information to a reading address register and control the read of a buffer memory in a page unit. CONSTITUTION:A burst header 6 of the packet is detected in the side of packet receiving parts 100-10n and the peculiar page control information are transferred to correspondent FIFO memories 170-17n in packet transmitting parts 270-27n. On the other hand, in the side of the packet transmitting parts 270-27n, the FIFO memories 170-17n to correspond to the transmitting page are selected on the basis of the page control information from the respective FIFO memories 170-17n and the address according to the removed page control information is transferred to a reading address register 19. Then, a buffer memory 13 is reading-controlled for the page unit. Thus, by using a software, the packet to be composed of plural bursts can be transmitted and received at high speed.
申请公布号 JPH01212144(A) 申请公布日期 1989.08.25
申请号 JP19880035194 申请日期 1988.02.19
申请人 NIPPON TELEGR & TELEPH CORP <NTT>;TOSHIBA CORP 发明人 KATAOKA HIDEKI;TAKAHASHI TATSURO;INABA AKIRA
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