发明名称 INTERFACE CIRCUIT TEST SYSTEM
摘要 PURPOSE:To make the false test of a high-speed transmission operation possible by selecting one of the tag-out false signal in a diagnosing register and a signal, which is obtained by folding a part of tag-in signals, and using the selected signal as a tag-out signal in case of test for the interface circuit. CONSTITUTION:A bus-out signal and the false signal of a tag-out signal are held in diagnosing bus-out register 5 of channel interface control part 1 and diagnosing tag-out register 6 respectively, and contents are set by the command of IOC logic part 2. When on-line designation control line 29 is turned on, bus-out 22 from the channel and tag-out signal line 23 are made available, and further, bus-line to the channel and tag-in signal line 25 are made available. Meanwhile, when line 29 is turned off, contents of registers 5 and 6 are applied to sequence control part 3 to stop bus-in and tag-out signals to the channel; and when folding designation control line 30 is turned on, a service-out false signal is applied to control part 3 to make false test possible.
申请公布号 JPS5580159(A) 申请公布日期 1980.06.17
申请号 JP19780154823 申请日期 1978.12.13
申请人 FUJITSU LTD 发明人 HIGUCHI TAIHOU;MUNAKATA AKIO
分类号 G06F11/22;G06F3/00;G06F11/00;G06F13/00 主分类号 G06F11/22
代理机构 代理人
主权项
地址