FET ONE-DEVICE MEMORY CELLS WITH TWO LAYERS OF POLYCRYSTALLINE SILICON

摘要

FET ONE-DEVICE MEMORY CELLS WITH TWO LAYERS OF POLYCRYSTALLINE SILICON Fabricating an integrated circuit array of FET one-device memory cells which includes providing a semisemiconductive substrate of a first conductive type; delineating field insulation regions; delineating polycrystalline silicon gate regions employing an oxidation barrier masking layer; introducing active impurities of a second and opposite conductive type into predetermined regions of the substrate to provide doped bit lines (FET drains), connection regions (FET sources), and lower conductive electrodes of the storage capacitors; next delineating upper poycrystalline silicon electrodes of the storage capacitors; growing silicon dioxide insulation over all portions of the structure except over the FET gate regions which are protected by the oxidation barrier masking layer; removing the oxidation barrier masking layer over the FET gates with an etchant; delineating contact holes to polycrystalline silicon capacitor electrodes and to FET sources and drains in circuits peripheral to the array of memory cells; and delineating the metallic-type high-conduc-tivity electrical interconnection word line pattern.