发明名称 FALSE FAULT GENERATION CONTROL SYSTEM
摘要 PURPOSE:To change arbitrarily a false fault generation position, a timing, etc., without treatments such as insertion of a special instruction into an operating program by utilizing the processing function of a sub-processing unit to control false fault generation. CONSTITUTION:An instruction address, an address which designated the set position of a false fault, and data which sets the generation timing of the false fault are set to data processing unit 1, and the instruction address to generate the false fault and the generation timing are held in stop address register 12 and timing data register 13 respectively. Independent storage program-type system control unit 2 is connected to this unit 1 through interface 15 to SMP, and the processing function of unit 2 is used to compare the false fault generation timing set in register 13 with the timing of an executing instruction by address comparator circuit 5 when unit 1 is executing the instruction of instruction address register 3, and a false fault signal is generated in a position designated by register 13.
申请公布号 JPS5580158(A) 申请公布日期 1980.06.17
申请号 JP19780154043 申请日期 1978.12.12
申请人 NIPPON TELEGRAPH & TELEPHONE 发明人 SHIRATA MITSUARI;MIYAGAWA JIYUNJI
分类号 G06F11/22;G06F11/00 主分类号 G06F11/22
代理机构 代理人
主权项
地址