发明名称 FLOATING-POINT DIVIDER
摘要 PURPOSE:To obtain an approximate inverse number without increasing an LSI even when table information are beyond memory capacity by providing a circuit for preparing higher 2 bits of approximate inverse and a table for lower 18 bits of approximate inverse (memory). CONSTITUTION:When the execution of a floating-point dividing instruction is started, a divisor to be set to a divisor register 2 is supplied through a digit normalizing circuit 4 to a divider 10 and supplied to a bit normalizing circuit 5. Then, a memory referring address is prepared to obtain the approximate inverse number. A table for lower 18 bits of approximate inverse 8 is referred according to addresses d2, d3...d11 and approximate inverses S3, S4...S20 are obtained. Then, according to the correspondence between the address and higher 2 bits of an inverse an S1 and an S2 are prepared in a circuit for preparing higher 2 bits of approximate inverse 7. Thus, approximate inverse numbers 1, S1, S2...S20 can be obtained. Then, since the approximate inverse can be obtained without increasing the number of the LSIs even when the table information to accompany the divisor are over the memory capacity, hardware quantity can be reduced.
申请公布号 JPH01217518(A) 申请公布日期 1989.08.31
申请号 JP19880042079 申请日期 1988.02.26
申请人 HITACHI LTD;HITACHI COMPUT ENG CORP LTD 发明人 HIYAMA KOICHI;ARAKI SHINOBU;TAKIGUCHI MAKOTO;WATANABE TAKESHI
分类号 G06F7/52;G06F7/483;G06F7/535 主分类号 G06F7/52
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