发明名称 INTERFACE SIGNAL RECEPTION CIRCUIT
摘要 PURPOSE:To eliminate the temporary level fluctuation or the malfunction caused by the noise by securing the hysteresis for the polarity inversion region. CONSTITUTION:The threshold levels of reception elements 11 and 12 are -3V and +3V respectively with a small amount of hysteresis. With input VIN of -5V, set and reset inputs S and R of flip-flop 14 feature the H and L levels each to secure the reset state. In case VIN is +1V, both inputs S and R feature the H level with preservation of the reset state. When VIN exceeds +3V, both elements 11 and 12 feature the output of the L level with the flip-flop set. After this, the reset state is kept although VIN may lower down to +3V--3V, and the state is not reset until VIN becomes under -3V. As a result, a large amount of hysteresis (-3- +3V) can be obtained as a whole, thus eliminating the malfunction.
申请公布号 JPS5578654(A) 申请公布日期 1980.06.13
申请号 JP19780151031 申请日期 1978.12.08
申请人 HITACHI LTD 发明人 TAKAKURA KENJI;YUGAWA YOSHIYUKI
分类号 H04L29/10;G06F13/00;H04L25/06 主分类号 H04L29/10
代理机构 代理人
主权项
地址