| 摘要 |
An address consists of a page address plus a block location address (one of 128) within the page; a cache memory can store 4 blocks (1 block = 4 words), from different pages, for each location address, in a data store 101, the page addresses of the stored blocks being stored in a directory 102. A control register 150 stores status signals for each location; 4 pending transfer bits and 4 full/empty bits for the 4 blocks, and a 2-bit last access pointer. A 4-bit failing block register indicates when a corresponding set of blocks through all 128 locations is failing. The signals from the control and failing block registers are combined to generate directly a signal which selects the next available block for replacement, on a first-in-first-out basis, when a fresh block is to be stored in the cache. <IMAGE> |
