发明名称 MAIN MEMORY UNIT
摘要 PURPOSE:To eliminate an idle state of an arithmetic unit by providing a write- information temporary memory circuit inside of a main memory unit. CONSTITUTION:Write-information temporary memory circuit 21 is provided inside of main memory unit 2, and write information from arithmetic unit 1 is temporarily stored in temporary memory circuit 20 within cycle time. Then, this temporarily- stored write information is written in the cycle time corresponding to the memory element. In this way, the idle time of arithmetic unit 1 is put into several cycles as if continuous write cycles were executed by main memory unit 2 in the cycle time of arithmetic unit 1. Arithmetic unit 1 makes use of this idle time put together so as to eliminate the idle state of arithmetic unit 1.
申请公布号 JPS5577068(A) 申请公布日期 1980.06.10
申请号 JP19780149950 申请日期 1978.12.06
申请人 HITACHI LTD 发明人 ISHII TAKAYOSHI
分类号 G06F12/06;G06F12/00;G11C7/00;G11C11/406;(IPC1-7):11C7/00 主分类号 G06F12/06
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