| 摘要 |
An N-channel silicon gate MOS read only memory or ROM formed by a process compatible with standard N-channel manufacturing methods but which allows the elimination of contacts between overlying metal or polysilicon lines and the semiconductor surface. Address lines are polysilicon, and output and ground lines are defined by N+ regions buried beneath field oxide. In the array, for each potential MOS transistor, a logic "1" or "0" is programmed by providing a thin oxide gate region beneath a polysilicon address line for one and providing thick field oxide for the other.
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