发明名称 PREPARATION OF SEMICONDUCTOR INTEGRATED CIRCUIT
摘要 PURPOSE:To heighten gate breakdown voltage, by continuing isotropic etching after providing a semiconductor substrate with a V-shape groove by anisotropic etching. CONSTITUTION:A p-epitaxial-layer is laminated on an n-type Si substrate, surface oxide film is etched by using a nitride film mask, and by making selective oxidation after B ion is driven in, a field oxide film 107 and a p-type reversion-preventing layer 106 are formed. It is again photo-etched and As ion is injected into thus exposed substrate to form an n<+>-layer 108 and to cover with an oxide film 109. Nitride film and oxide film in channel section are removed and etched anisotropically. As the V-shape groove's tip is sharp, dielectric resistance of the gate film is extremely deteriorated, and therefore, the tip is rounded by isotropic etching. And then, a gate oxide film 112 and a gate electrode 113 are provided and covered with PSG114, and an Al electrode 115 is provided. It is possible, in this mechanism, to prevent electric field from gathering to the V-shape groove's tip and to raise the gate film's dielectric resistance to an extremely high value.
申请公布号 JPS5577176(A) 申请公布日期 1980.06.10
申请号 JP19780151632 申请日期 1978.12.07
申请人 发明人
分类号 H01L29/06;H01L21/306;H01L21/336;H01L29/423;H01L29/78 主分类号 H01L29/06
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