| 摘要 |
A combination of one or more shift registers with a binary counter and a memory device is disclosed wherein binary information inputs are supplied to the shift register through a plurality of AND gates which also receive inputs from a pulse generator and the output of the shift register is supplied through a second plurality of AND gates to a storage device, and wherein the binary counter supplies inputs to the second plurality of AND gates, and wherein the pulse generator supplies outputs to the shift register, the binary counter and to the first plurality of AND gates. A second embodiment provides a plurality of shift registers which receive outputs from the first shift register and are connected to a plurality of memories through additional AND gates which are controlled by the pulse generator and the associated shift register. |
