| 摘要 |
PURPOSE:To elevate access time of the memory of SOSMOS FET configurations by connecting the bit lines to the power supply through several series transistors. CONSTITUTION:The bit lines B1 and B2 are connected to the power supply Vcc in series of the respective several transistors such as two, etc. controlled by the inversion enable signal, by the types of FETQ9 and Q9'-Q12 and Q12', and the pre-charge potential of the lines B1 and B2 becomes the voltage potential of the difference of the power supply and two times of the threshold voltage of each FETQ9-Q12 and Q9'-Q12'. Accordingly, even if case of SOSMOSFET configurations by which the semiconductor layer always becomes a depletion layer due to a thin semiconductor layer of the gate oxide film, the access time is shortened through the bit lines which are pre-charged to the fittest potential. Resulting from the foregoing, the access time of the SOSMOSFET memory is elevated. |
