发明名称 PREPARING INTERPOLATION TYPE MOS SEMICONDUCTOR DEVICE
摘要 PURPOSE:To provide a high degree of intergration by a method wherein opening are made on the SiO2 film on p and n-type diffusion layers and, after injection of the same type impurity ions, the openings are stacked with semiconductor layer and wiring layer. CONSTITUTION:In a CMOS device, openings are made on the SiO2 film on an Si substrate in which source and drain layers have been formed on the p-type and n- type areas. The openings expose p and n-type layers, on which the same type impurity ions are injected respectively to form diffusion layers 5a, 6a. Then, the openings are provided with adition-free polycrystalline Si 11 and Al wiring 1 in double layers. Although Si diffuses into Al, the Si is supplied from the Si layer 11 and therefore the diffusion layers 5, 6 are completely unaffected, thereby providing a good pn-junction property. Even when the openings are shifted from the layers 5, 6, the ion injection layers 5a, 6a formed on the substrate 3 at the locations of the openings prevent short-circuit failures. As such, the process prevents alloy spike, and provides shallow diffusion layers and compactly sized elements.
申请公布号 JPS5574175(A) 申请公布日期 1980.06.04
申请号 JP19780147605 申请日期 1978.11.29
申请人 NIPPON ELECTRIC CO 发明人 KAWAMATA IKUO
分类号 H01L29/08;H01L21/28;H01L21/8238;H01L27/092;H01L29/78 主分类号 H01L29/08
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