| 摘要 |
PURPOSE:To reduce the area of memory cell noticeably by arranging a MIS construction diode, and address line and a digit line on the semiconductor substrate to function as a bipolar transistor. CONSTITUTION:A p-type well region 12 and a p-type low resistance buried region 15 acting as the address line are formed by diffusion on an n-type semiconductor substrate 11 separated at a given distance from each other, and covered with an insulator layer 14 to make a MIS construction. Besides the regions 12 and 15, the substrate exposed is coated with a thick field insulator layer 16. A voltage conducting layer 13 acting as a surface side electrode for the MIS construction diode is formed on these layers 14 and 16 in such a manner as to serve as the digit line. With such an arrangement, the substrate 11, the portion other than an inversion layer on the region 12 and the inversion layer 17 generated on the surface of the region 12 each function as the emitter, base and collector electrodes 21, 22 and 27 of an npn transistor. |
