| 摘要 |
PURPOSE:To prevent the lowering of data transmission amount and long time transmission of data in error, by detecting the specific bit pattern information included in normal data and matching the synchronism of sub-data based on the detected signal. CONSTITUTION:The ''00'' pattern included in 5-bit data of output of serial-parallel shift register 41 is detected at the detection circuit 5. Further, based on the ''00'' pattern detection output, conversion clock signal and sub-data synchronizing signal, reset signal is produced from the signal generation circuit 6 and it is fed to the 1/4 frequency division circuit 46 to match the synchronizing timing of the sub-data synchronizing signal to the data. On the other hand, the 5-4 conversion data of ROM42 addressed with 5-bit parallel data of the register 41 is read out as 4-bit parallel data and fed to the parallel serial shift register 43. Thus, the demodulation data latched is obtained from the output from the circuit 46. |
