发明名称 BLOCK SWITCHING SYSTEM FOR MEMORY UNIT
摘要 PURPOSE:To increase the deficiency relieving ability with less limit of switching from the basic unit to the redundancy unit, by providing the switching gate circuit to the switching control circuit, in the unit switching between the basic and redundancy in group unit. CONSTITUTION:Among the address information from the system, the group address information is given to the switching display element registration memory 201 via the bus 200, and a given information is set to the read-in data register 202. Further, the information of the switched block address display fields C-1 and C-2 is given to the switching gate circuit 203, which supplies the information of C-1 or C-2 to the switching gate 222 via the bus 205 as the address of the redundancy unit, based on the block control signal of system from the bus 204. The circuit 222 outputs the set address information of the bus 200 or 205 based on the control signal on the line 221. As a result, the deficient block in the set is avoided to perform switching.
申请公布号 JPS5570998(A) 申请公布日期 1980.05.28
申请号 JP19780143196 申请日期 1978.11.20
申请人 NIPPON TELEGRAPH & TELEPHONE 发明人 MASUDA KIYOSHI;EGAWA HIROSHI
分类号 G06F12/16;G06F11/16;G11C29/00 主分类号 G06F12/16
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