发明名称 ERROR PROTECTION SYSTEM
摘要 PURPOSE:To ensure an error protection for the input featuring a short duration, the short break and others by applying the majority protection method to the input obtained continuously and thus securing the continuance of the input. CONSTITUTION:Primary test result 10 obtained continuously is shifted by one bit at circuit means 1, and the 2/3-majority protection is given for the error protection to the short break against the three-times primary test results of continuous 20, 21 and 22 among the output of means 1 to obtain the result of 30. Then the 2/3-majority protection is also applied to the last twice tests 21 and 22 among the above- mentioned three-times test results as well as to the three-times of primary test result 23 obtained next, resulting in 31. Then an AND is secured to decision results 30 and 31 to which the protection is given for the short break in order to confirm the continuance, thus resulting in 40.
申请公布号 JPS5567854(A) 申请公布日期 1980.05.22
申请号 JP19780140333 申请日期 1978.11.14
申请人 NIPPON ELECTRIC CO;NIPPON TELEGRAPH & TELEPHONE;OKI ELECTRIC IND CO LTD;HITACHI LTD;FUJITSU LTD 发明人 FUKUI AKIRA;IMAGAWA HITOSHI;KAWAGUCHI MASAHARU;HIROSE KAZUTO;OOSAKI TAKAAKI
分类号 G06F11/00;G06F11/08;G06F11/14 主分类号 G06F11/00
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