| 摘要 |
PURPOSE:To obtain a phase detector for PLL suitable for the control of a resonance tracking circuit system, etc., by inhibiting generation of signals of a phase error over 180 deg.. CONSTITUTION:Assuming that phases of input signals R and V have relations of (a) and (b), output (P7) of gate 9 resets FFs 6 and 7 to set an initial state in case of a L level, and therefore, (P7) is L and FFs 6 and 7 are reset during times t1- t2; and when input signal R becomes H-level at time t2, FF 6 is set to perform phase error detection of detection mode (mode 1) within 180 deg.. Even if FFs 6 and 7 are reset at time t4 by causes sucy as noise during operation and FF 7 is set at time t4+DELTAt to start the detection operation of detection mode (mode 2) over 180 deg., FF 7 is reset again at time t5-t6, so that detection of mode 1 can be performed by setting FF 6 again from time t6. |
