| 摘要 |
A binary coded signal is converted into pseudoternary coded form not by a complicated amplitude-modulation technique, but instead by application to a combination of flip-flops and logic gates. A clock pulse train, to which the binary coded signal is phase synchronized, is used to generate component pulse trains some of whose signal elements have only one half the duration of the bits of the binary coded signal. These component pulse trains are then combined to form the pseudoternary coded signal, in which some bits of the binary signal are represented by combinations of signal elements each having only half the bit duration and different respective ternary logic levels. |
