发明名称 PREPARATION OF SEMICONDUCTOR INTEGRATED CIRCUIT
摘要 PURPOSE:To enable the coexistence of a I<2>L (Integrated Injection Logic) and a bipolar transistor by conducting heat treatment for oxidization at temperatures that provide a different rate of oxidization due to the difference of concentration near the surface of semiconductor. CONSTITUTION:An n-type epitaxial layer 2 is grown on a p-type substrate 1 through an n<+> embedded layer 4, and then a dielectric 18 of oxide film or nitriding film on its surface is removed by etching. After masking it, n-type impurities are diffused up to the required depth to form a high concentration n-type layer 12. In the next step, if the temperature for thermal oxidization is lowered, the rate of oxidization in the layer 12 becomes more rapid than that of others. As the result, a step is formed on the surface thereof. Next, an oxide film 13 is removed, and then the high concentration n-type layer is dispersed through high temperature treatment at a time when the isolation and others are formed to lower the concentration near its surface, thereby forming the I<2>L and the bipolar transistor by means of conventional method. In this arrangement, the epitaxial layer of I<2>L becomes thinner to improve a current amplification factor thereof, whereas the high dielectric strength of the bipolar transistor can be maintained to enable the coexistence of them.
申请公布号 JPS5563838(A) 申请公布日期 1980.05.14
申请号 JP19780137323 申请日期 1978.11.09
申请人 TOKYO SHIBAURA ELECTRIC CO 发明人 SASAKI HAJIME;TAGUCHI MINORU;FURUKAWA AKIHIKO;KANZAKI KOUICHI
分类号 H01L21/8226;H01L21/316;H01L21/331;H01L21/761;H01L27/02;H01L27/082;H01L29/73;H03K19/091 主分类号 H01L21/8226
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