| 摘要 |
1363171 Soldering INTERNATIONAL BUSINESS MACHINES CORP 30 Aug 1972 [14 Oct 1971] 40156/72 Heading B3R [Also in Division H1] An interconnection package comprises plural laminar dielectric layers 10, 12, 14, 16, e.g. of epoxy glass, of which a ground plane comprises layers 18, 20 of Cu sandwiching an interconnecting Ga layer 22. Interconnection circuit patterns 26, 28 of Cu are separated by dielectric layer 30 and defined by selective etching, and plural studs 32 or plated through holes provide vertical conductive paths bonded by, e.g. Ga at 34 (Fig. 1). In processing (Fig. 2, not shown) the insulant member of, e.g. epoxy glass, ceramic, quartz, polyamide glass, polyethylene terephthalate is perforated, and conductive material, e.g. Cu is plated in the holes to form a stud. Adjacent members with studs therein are conjoined with liquid Ga at the interface and heated under pressure to interdiffuse the Ga and Cu and form a solid bond therebetween. Conductive planes can be similarly bonded, and the studs may terminate coplanar with the surface of the members. Dielectric sections may be conjoined (Fig. 3, not shown) with vertical interconnection paths as above, and horizontal metallized patterns thereon separated by a similar dielectric layer 82. The conductive paths may be of Au, Ag, Ni instead of Cu. |
