| 摘要 |
<p>PURPOSE:To prevent degradation of the storage state of a memory and simplify peripheral circuits by constituting a circuit so that a read signal output may be generated only when an address selection signal is applied to the address input terminal. CONSTITUTION:The address selection signal applied to terminal 4 is applied to AND gate circuits 81-8n and is inputted to address decoder circuit 2 by the address input enable signal applied to terminal 15 at a read time. Then, the output of circuit 2 is applied to one input terminals of AND gate circuits 71-7n, and further, the output of OR gate circuit 9 is applied to the other input terminals of circuits 71-7n. Meanwhile, in case that the logical level at input terminal A of AND gate circuit 10 becomes ''1'' at time t1 by the signal applied to terminal 15, the logical level at input terminal B becomes ''0'' at time t2 after time t1. Therefore, pulse signals are generated at output terminal C of circuit 10 from time t1 to time t2. By using these signals as read signals, read signals can be generated automatically only at an address selection time.</p> |
