发明名称 SAMPLING HOLD CIRCUIT
摘要 PURPOSE:To increase channels in number by selectively connecting two holding capacitors and output amplifiers in sequence. CONSTITUTION:The alternative switching of selective switches 22i and 22o of sampling hold circuit 20 arranges sampling timing Sij and holding timing Hij like S11H11S12H12... and S21H21S22H22... as shown in Fig B. In this case, low-speed and low-priced amplifiers 11 and 14 may be used and capacitors 13-1 and 13-2 can be charged and discharged for a sufficiently-long period, so that evil influences of follow-up and cross- talk will never be exerted.
申请公布号 JPS5560358(A) 申请公布日期 1980.05.07
申请号 JP19780133132 申请日期 1978.10.31
申请人 FUJITSU LTD 发明人 TOMITA YOSHIHIRO;TSUDA TOSHITAKA
分类号 G11C27/02;H04B14/04;H04J3/00;H04J3/04 主分类号 G11C27/02
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