| 摘要 |
PURPOSE:To operate a peripheral device at the optimum timing not depending on the dispersion of the transition time of an output signal by outputting a signal representing the determination of the output signal to the outside when the signal level of an output pin coincides with an output address signal in the inside of an LSI. CONSTITUTION:Address signals (a0-a31) on an internal bus are latched at a latch means LT by a timing signal phi2 via a transfer MOSQt of each of drivers (ADR0-ADR31). The signal is outputted to the output pins (A0-A31) after its driving force is increased by inverters INV3 and INV4 of two stages, however, the rise time of the signal is different according to load capacitance (C0-C31). The signals of the output pins (A0-A31) and that of the latch means LT are monitored by an EOX circuit, and when coincidence are obtained in all of the pins, the output of an OR gate G0 goes to a level '0', and a determination signal is outputted to the outside. |
