| 摘要 |
<p>Operate/release timing circuits are employed to generate time delayed pulse signals employed, for example, in telecommunications signaling systems. Pulse position and pulse width errors and other problems are resolved by employing a single digital counter (15) and associated control logic elements. Input signal pulse break, gap and the like immunity is achieved by controlling (via 16, 23, 40, etc.) the counter (15) to count up for a predetermined interval (detected via 24) regardless of the presence (high state) or absence (low state) of the input pulse signal (M). Once a valid input pulse has been detected and is terminated a timer output change of state is delayed for a so-called release delay interval. Once the pulse signal has terminated for a predetermined integrated interval (detected via 26) the counter (15) is controlled (via 16, 20, 38, 46, etc.) to continue counting down until the initial condition (zero count) is reached regardless of the presence (high state) or absence (low state) of the input pulse signal (M). </p> |
