发明名称 DATA PROCESSING SYSTEM
摘要 A data processing system includes, e.g. four memory blocks (MB0-MB3) each of which stores two different word lengths, e.g. two thousand 18-bit words (EAO) and sixty-two thousand 16-bit words (A). The shorter 16-bit words are instructions with a 9-bit address part (V) which allows any one of a subset (EAO(SO)) of the 18-bit words in the same memory block to be addressed. The resulting accessed 18-bit word is used as an indirect address to any word in any one of the four memory blocks. Thus a processor based on 16- bit words may access a memory which is four times larger than the sixty-four thousand word memory usually regarded as the upper limit in a 16-bit processing system. The remaining subset (EAO(SI)) of 18-bit words not used for indirect addressing can be used for data. As 64K memories with 18 bits are not commercially available it is contemplated that 64K memories of 16-bit words be used with two 64K memories of 1 bit each to make up the 18 bit words. <IMAGE>
申请公布号 ZA7901924(B) 申请公布日期 1980.04.30
申请号 ZA19790001924 申请日期 1979.04.23
申请人 ISEC 发明人 DE VOGHT C;YSSELDYK J;BAUWENS J
分类号 G06F9/355;G06F12/04;G06F12/06 主分类号 G06F9/355
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