| 摘要 |
PURPOSE:To make it possible to restore a logic state, destroyed by a test, into an original state by providing a shift memory circuit stored with shift-in and shift-out start addresses and data length data, data buffers and a re-edition memory circuit. CONSTITUTION:In accordance with a shift-in start address and data length stored in shift memory circuit 20, sequence circuit 1 which divide data into several partitions extracts test pattern data from circuit 13 to data buffer 21 by a test instruction from test pattern memory circuit 13. This data is shifted in shift register 2 and processed by external data and its result is sent to data buffer 22, where is compared with a correct value by shift-out output comparator circuit 17. In this case, since the both disagree, data in buffers 21 and 22 are edited again and stored by re- editing memory circuit 23, whose contents are inputted to buffer 21 for a reshift-in. Consequently, a logic state, destroyed by the test, can be restored into a stage before a shift-out, simplifying the pointing-out of a fault part. |
