| 摘要 |
PURPOSE:To realize the low power consumption as well as to accelerate the logic velocity by setting the absolute value of the gate driving voltage of plural number of MOS transistors in the P-type MOS circuit larger than the absolute value of the 1st power voltage and then securing the parallel connection to the 2nd power source of the negative polarity. CONSTITUTION:P-channel MOS circuit 13 of one circuit is selected from four circuits of each set based on the page selection data. At the same time, the complementary MOS-type dynamic NAND logic circuit is formed with N-channel MOS transistor Tr15, P-channel MOSTr17 and capacity 16 each. On the other hand, one decoder line is set at a high level with the other line set at low level each for address decoder 11. And one terminal of line 12 is connected to N-channel MOSTr18, and the other terminal is connected to P-channel MOSTr19 each. Here the absolute value of each source in Tr18 is set larger than that of the voltage of power source VDD1, and also each source is connected in parallel to power source VDD2 of the negative polarity. As a result, the power consumption can be reduced for the device, at the same time increasing the logic velocity. |
