| 摘要 |
<p>BALANCED SYNCHRONOUS DETECTOR CIRCUIT A balanced synchronous detector circuit for detecting the amplitude of a received signal and for detecting the phase difference between the received signal and a generated signal. A preferred application of this balanced synchronous detector circuit is in a stereo decoder of the type used for receiving and decoding a composite stereo signal. When so used, the balanced synchronous detector circuit receives the pilot signal normally included in the composite stereo signal and also receives locally generated signals for the purpose of generating outputs proportional to the amplitude of the received pilot signal and proportional to the phase difference between the pilot signal and the locally generated signal. These outputs can be used to control a phase-locked loop for generating the local signal and also for indicating the presence of a stereo transmission. The balanced synchronous detector circuit includes a first double-balanced modulator having a first section provided with a first set of input terminals to which the received signal is applied and a second section provided with a second set of input terminals to which the locally generated signal is applied. The balanced synchronous detector circuit further includes a second double-balanced modulator having a first section formed of a portion of the second section of the first double-balanced modulator and a second section provided with a set of input terminals to which another locally generated signal is applied. An output signal derived from the second section of the second double-balanced modulator is proportional to the amplitude of the received signal, and an output signal derived from the second section of the first double-balanced modulator is proportional to the phase difference between the received signal and the locally generated signal. -ii-</p> |
