| 摘要 |
PURPOSE:To obtain an elastic store circuit which realizes reduction of the absolute delay amount as well as the high-speed operation by detecting the phase difference between the writing and reading pulses and thus controlling the generation of the both pulses. CONSTITUTION:The fact that the writing pulse of the control row line approaches from the back o the reading pulse of the control row line is detected by D-F/F71-74 of the left side. While the fact that the writing pulse of the control column line approaches from the back of the reading pulse of the control column line is detected by D-F/F75-78 of the upper side. The both detection signals are connected to NAND gate NA1 via signal lines 87 and 88 to detect the fact that the writing pulse of an optional memory cell approaches from the back of the reading pulse to overlap it via D-F/F28's output IR terminal 4. In other words, the state under which the data is written into all memory cells, that is the data full state can be detected through the fact that IR terminal 4 becomes ''0''. In exactly the same way, the state under which the data of all memory cells are read out, that is, the data-empty state can be detected by the fact that OR terminal 6 becomes ''0''. |
