发明名称 Clock-pulse train monitoring circuit - compares input clock pulse train pattern with stored control train pattern to detect differences
摘要 <p>The monitoring circuit has a single test line (b) connected to the clock pulse output lines (A1, An), in order to detect faults in the time sequence of the pulse trains appearing on these lines. The pulse sequence on the test line is compared (Vg) with the time characteristics of the control signals of fixed format used for originally generating these pulses. If there is a difference in a characteristic (time at which a pulse or pulse interval occurs, a fault signal is transmitted (GD, GA, GZ). The system enables monitoring of clock pulse train on a single line, one which the actual pulse trains are fed to the components.</p>
申请公布号 DE2842350(A1) 申请公布日期 1980.04.17
申请号 DE19782842350 申请日期 1978.09.28
申请人 SIEMENS AG 发明人 DIETL,RUDOLF;EISL,ENGELBERT
分类号 H03K5/26;H04M3/24;H04M15/00;(IPC1-7):H03K5/18;H04Q1/22 主分类号 H03K5/26
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