| 摘要 |
PURPOSE:To simplify address generation for a complex pattern by improving efficiency of utilization of hardware by generating its address by freely fetching a fixed value in an arithmetic circuit with several fixed registers shared. CONSTITUTION:An initial value set to fixed registers 4Hl-4Hn and 4Dl-4Dn and a random fixed value of a increment coefficient are supplied to arithmetic circuits 5a-5c, arithmetic results of which are stored in output registers 6a-6c. Consequently, addresses are generated from registers 6a-6c and access to memory element 2 for matrix formation is attained through sense amplifiers 3a and 3b and address decoders 2a and 2b. This constitution eliminate the need to change the set value of fixed registers in real time and efficiency of utilization of hardware will improves, so that addresses of a complex pattern can easily be generated. |
