| 摘要 |
A field access type bubble memory system has a major loop (304) -minor-loop (302) configuration and a fault tolerant memory device comprising at least one redundant loop (320, 322, 324), a stationary register (312) having at least as many register positions as the total number of minor loops (302) to act as a flaw table, and combining means (344) coupled with said major loop (304) and said stationary register (312) so that the contents of said stationary register (312) and said major loop (304) may be combined whereby defective minor loops (302) may be disregarded and nominal memory capacity retained. In another embodiment the major loop data bits and flaw table bits are interleaved on a common output conductor. <IMAGE> |
