| 摘要 |
PURPOSE:To simplify circuit constitution by reducing a chip size in case of IC-implementation by driving cascaded one-bit shift registers by a single clock signal. CONSTITUTION:One-bit shift registers 201-208 are cascaded and supplied with single clock signal phi in parallel, and an output from final-stage register 208 is fed back to initialstage register 201 through control gate logic circuit 21 supplied with a control signal. Those registers 201-208 are provided with a circuit of N-type FETs 25 and 26 connected in series between power supply Vss and output terminal 24 and that of P-type FETs 27 and 28 connected in series between power supply VDD and output terminal 24. Gates of those FETs 26 and 27 are connected for input terminal 29, and those of FETs 25 and 28 are also connected to obtain an input termianl for clock signal phi, so that prior-stage and post-stage clock inverters 22 and 23 will be constituted. Then, registers 201-208 are driven by single clock signal phi. |
