发明名称 Clock pulse generator comprising identical generating circuits - produce staggered series of pulse trains and prevents faulty circuit affecting others
摘要 <p>The clock pulse generator consists of identical generating circuits connected sequentially to produce a staggered series of output pulse trains. If a fault develops in one circuit the circuits preceding and following it are unaffected. The outputs of the faulty circuit are connected together to the appropriate output of a substitute clock. Each circuit has a shift register logic gates, a monitor and output amplifiers. Two clock pulse sources serve the first circuit. The second circuit is served by the output of the first and the third by the output of the second and so on.</p>
申请公布号 DE2842373(A1) 申请公布日期 1980.04.10
申请号 DE19782842373 申请日期 1978.09.28
申请人 SIEMENS AG 发明人 DIETL,RUDOLF;EISL,ENGELBERT
分类号 H04M15/00;(IPC1-7):H04M19/00;H03K5/15 主分类号 H04M15/00
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